DVB-C2 (Digital Video Broadcasting for Cable 2) is a second-generation digital cable broadcasting standard in Europe (Non-Patent Document 1).
On the transmission side of a transmission system compliant with DVB-C2, signals of a Header portion are generated by performing mapping after copies of the same information are made. Headers specified in DVB-C2 include Robust Headers and High Efficiency Headers, which use different modulation methods.
FIG. 1 is a diagram showing a method of generating a Robust Header. Sixteen signaling bits (information) to be transmitted as a Header portion are input to a generating unit that generates Robust Header signals.
An RM (32, 16) encoder 11 performs RM encoding on the 16 signaling bits of the Header portion, and outputs a 32-bit RM code word. The RM code word is then copied and divided into an upper branch and a lower branch.
In the lower branch, the RM code word that is output from the RM (32, 16) encoder 11 is input to a cyclic shifting unit 12. The cyclic shifting unit 12 cyclically shifts each of the input bits, and outputs each of the resultant bits. Where the respective bits that are input to the cyclic shifting unit 12 are bit0, bit1, bit2, . . . , and bit31 in the order of input, the cyclic shifting unit 12 outputs bit30, bit31, bit0, bit1, bit2, . . . , and bit29 in this order.
A scrambling unit 13 subjects each of the bits output from the cyclic shifting unit 12 to an exclusive-OR operation with a 32-bit sequence defined in the standard, and outputs the operation result as a RM code word from the lower branch to a QPSK mapper 14.
Based on the RM code word from the upper branch and the RM code word from the lower branch, the QPSK mapper 14 performs QPSK mapping as specified in the standard, and outputs a Robust Header formed with 32 QPSK symbols.
FIG. 2 is a diagram showing a method of generating a High Efficiency Header. Of the components shown in FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1. Sixteen signaling bits to be transmitted as a Header portion are input to a generating unit that generates High Efficiency Header signals.
An RM (32, 16) encoder 11 performs RM encoding on the 16 signaling bits of the Header portion, and outputs a 32-bit RM code word. The RM code word is then copied and divided into an upper branch and a lower branch.
In the lower branch, the RM code word that is output from the RM (32, 16) encoder 11 is input to a cyclic shifting unit 12. The cyclic shifting unit 12 cyclically shifts each of the input bits, and outputs each of the resultant bits. Where the respective bits that are input to the cyclic shifting unit 12 are bit0, bit1, bit2, . . . , and bit31 in the order of input, the cyclic shifting unit 12 outputs bit30, bit31, bit0, bit1, bit2, . . . , and bit29 in this order.
A scrambling unit 13 subjects each of the bits output from the cyclic shifting unit 12 to an exclusive-OR operation with a 32-bit sequence defined in the standard, and outputs the operation result as a RM code word from the lower branch to a 16-QAM mapper 21.
Based on the RM code word from the upper branch and the RM code word from the lower branch, the 16-QAM mapper 21 performs 16-QAM mapping as specified in the standard, and outputs a High Efficiency Header formed with sixteen 16-QAM symbols.
According to DVB-C2, those Headers are used as Preamble Headers and FEC Frame Headers. Only Robust Headers are used as Preamble Headers, and Robust Headers or High Efficiency Headers are used as FEC Frame Headers.
A receiver is able to determine the position of a Preamble Header from absolute frequency. The only role of a Preamble Header is to transmit 16 signaling bits.
Meanwhile, the position of an FEC Frame Header can be determined from either absolute frequency or L1 signaling part 2 (L1 information), which is transmission control information. An FEC Frame Header is used by a receiver not only to transmit 16 signaling bits but also to detect the position of an FEC Frame.
FIG. 3 is a diagram showing the structure of a receiver specified in the Implementation Guidelines (Non-Patent Document 2). FIG. 3 shows a structure that receives Robust Headers.
A QPSK de-mapper 31 receives the 32 QPSK symbols of a Header portion that are sequentially input, and performs soft-decision de-mapping. The QPSK de-mapper 31 divides the bits of a predetermined width obtained through the soft-decision de-mapping into an upper branch and a lower branch, and outputs the resultant bits.
In the lower branch, a descrambling unit 32 subjects the output of the QPSK de-mapper 31 to an exclusive-OR operation with a 32-bit sequence that is defined in the standard and is the same as the sequence used on the transmission side, and outputs the operation result.
The respective bits that are output from the descrambling unit 32 are input to a cyclic shifting unit 33. The cyclic shifting unit 33 cyclically shifts each of the input bits in the reverse order of the order in which cyclic shifting has been performed on the transmission side, and outputs each of the resultant bits. Where the respective bits that are input to the cyclic shifting unit 33 are bit30, bit31, bit0, bit1, bit2, and bit29 in the order of input, the cyclic shifting unit 33 outputs bit0, bit1, bit2, . . . , and bit31 in this order.
A combining unit 34 combines the upper-branch bits with the lower-branch bits supplied from the cyclic shifting unit 33, and outputs the combination result. According to the Implementation Guidelines, a maximum capacity can be achieved when the combining is performed with an output of a soft-decision de-mapper.
An RM decoder 35 performs RM decoding on the output of the combining unit 34, and outputs 16-bit signaling data.
FIG. 4 is a block diagram specifically showing the structure shown in FIG. 3. Of the components shown in FIG. 4, the same components as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3.
A controller 41 generates a signal uen0 that is a control signal (EN) for a flip-flop 42, and a signal uen1 that is a control signal for a flip-flop 43. The controller 41 also generates a signal len0 that is a control signal for a flip-flop 44, and a signal len1 that is a control signal for a flip-flop 45. The controller 41 generates a signal lsel that is a select signal for a selector 46, and a signal den that is a control signal for flip-flops 51-0 through 51-30.
The QPSK de-mapper 31 receives the 32 QPSK symbols of a Header portion that are sequentially input, and information indicating the 32 reception states of those symbols, and performs soft-decision de-mapping on the QPSK symbols based on the reception states. The QPSK de-mapper 31 divides the bits obtained through the soft-decision de-mapping into an upper branch and a lower branch, and outputs the resultant bits. The bit width of the output of the QPSK de-mapper 31 is represented by n.
In the upper branch, the flip-flops 42 and 43, which are flip-flops with EN, delay the output of the QPSK de-mapper 31 in accordance with the signals uen0 and uen1 generated by the controller 41. The output of the QPSK de-mapper 31 delayed by the flip-flop 43 is supplied to the combining unit 34.
In the lower branch, the descrambling unit 32 subjects the bits supplied from the QPSK de-mapper 31 to an exclusive-OR operation with a 32-bit sequence that is defined in the standard and is the same as the sequence used on the transmission side, and outputs the operation result.
The respective bits that are output from the descrambling unit 32 are supplied to the selector 46 and the flip-flops 44 and 45. The flip-flops 44 and 45 store the output of the descrambling unit 32, and supply the output to the selector 46 in accordance with the signals len0 and len1 generated by the controller 41.
The selector 46 selects the output of the descrambling unit 32 when the signal lsel generated by the controller 41 is 0, selects the output of the flip-flop 44 when the signal lsel is 1, and selects the output of the flip-flop 45 when the signal lsel is 2. The bits selected by the selector 46 are supplied as the lower-branch bits to the combining unit 34.
Where the respective bits that are output from the descrambling unit 32 are bit30, bit31, bit0, bit1, bit2, . . . , and bit29 in the order of output, the selector 46 outputs bit0, bit1, bit2, . . . , and bit31 in this order. The timing for the first bit bit0 to be output from the selector 46 and the timing for the third bit bit0 to be output from the flip-flop 43 are the same.
The combining unit 34 combines the upper-branch bits, which are the output of the flip-flop 43, with the lower-branch bits, which are the output of the selector 46, and outputs the combination result. The bit width of the output of the combining unit 34 is (n+1) bits.
The output of the combining unit 34 is supplied as symbol31 to the RM decoder 35, and is sequentially stored into the flip-flops 51-0 through 51-30, which are 31 flip-flops with EN. The output of the combining unit 34 stored in the flip-flops 51-0 through 51-30 is output as symbol0 through symbol30 to the RM decoder 35 in accordance with the signal den generated by the controller 41.
The RM decoder 35 performs RM decoding on the information equivalent to the 32 symbols formed with the outputs of the flip-flops 51-0 through 51-30, which are the 31 flip-flops, and the output of the combining unit 34, and then outputs 16-bit signaling data.